--- Log opened Сбт Сен 23 00:00:03 2006
--- Day changed Сбт Сен 23 2006
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03:11 < marcheu> does this new driver have interesting (i.e. from a RE viewpoint) properties ?
03:11 < darktama> marcheu: not that I know of, I just hope it works on my C51 :)
03:12 < darktama> I get a black screen and need to reboot on my nv40.. so 8774 it is for that card
03:13 < marcheu> haha duke said the same
03:13 < marcheu> I have a gf2 mx as well :)
03:14 < darktama> ahh, just read the backscroll - exact same thing here
03:17 < darktama> any progress on the VT issue?
03:17 < marcheu> no, I'm working on context switching
03:17 < darktama> cool, that's more worthwhile anyway :P
03:17 < marcheu> I was pondering comitting my broken changes but I didn't
03:17 < marcheu> I think I'll commit when I stop getting fifo errors interrupts
03:18 < marcheu> I also get the crash when quitting X
03:18 < marcheu> happens each time there is activity on the screen, 100% reproducible
03:18 < darktama> hmm, I might try a bit harder to reproduce it soon
03:18 < marcheu> well I can commit now if you like
03:19 < marcheu> I'm not sure my drm is in a "commitable" state, though
03:19 < darktama> hehe, mine neither at the moment :)
03:19 < marcheu> but yeah, maybe you'll see some (hopefully) obvious mistake then
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04:25 < marcheu> darktama: where does the "RAMIN+0x11000 0.5k" come from ?
04:25 < marcheu> esp the 0.5k part
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04:26 < darktama> the 0.5k part is from a comment in haiku, +0x11000 is because of 0xXXXXX110
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04:26 < marcheu> yeah the +0x11000 was pretty clear :)
04:27 < darktama> btw, I think RAMFC is different on nv40 - it either doesn't exist, or is setup differently
04:27 < darktama> PFIFO_RAMHT always reads 0, even if you put other values in there
04:27 < marcheu> NV_PGRAPH_NV40_UNK220 might be related ?
04:28 < darktama> not sure, that just has a dma object covering all of video memory
04:28 < marcheu> was wondering since it's initialized at the same time..
04:28 < darktama> I have a suspicion 0x2220 is related (the reg after PFIFO_RAMRO)
04:29 < marcheu> hmm it's not among the "interesting" regs
04:30 < marcheu> I really shoudl fix that test, it gives very useful information to have regs from different cards available
04:31 < marcheu> anyway, I suppose this stuff goes to VRAM as usual
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05:31 < marcheu> hmm is our context dma object offset always 0
05:31 < marcheu> ?
05:32 < darktama> eh?
05:33 < marcheu> ah no it's not :)
05:33 < marcheu> just a stupid question
05:39 < marcheu> hmm why are the NV10+ region regs named NV_FB_TILE_NV40 ?
05:42 < darktama> hm, no idea.. who named them?
05:44 < marcheu> dunno... I'll fix it anyway$
05:52 < marcheu> do we have any information on DmaFetchTrigger/DmaFetchSize/DmaFetchMaxReqs ?
05:53 < darktama> not a lot I don't think
05:54 < marcheu> hmm we should see what typical values are
05:54 < darktama> do we touch them at all yet?
05:54 < marcheu> I'm adding it right now
05:55 < marcheu> each fifo has this information in RAMFC
05:56 < marcheu> I suppose it's similar to NV_PFIFO_CACHE1_DMA_FETCH
05:57 < darktama> yup, iirc nvosdk simply pulls the info out of RAMFC and puts it in PFIFO
05:57 < marcheu> ah, good
06:00 < marcheu> I suppose we'll play with it later on for extra performance...
06:04 < darktama> hmm, what is the default btw?
06:05 < marcheu> hmm let me see
06:05 < marcheu> TRIG_112_BYTES
06:06 < marcheu> SIZE_128_BYTES
06:06 < marcheu> MAX_REQS_4
06:06 < darktama> hmm, I guess the trigger would effect when the GPU considers a channel worthy of being switched to
06:07 < marcheu> yup, anyway if it can even work with current values I'll be a happy camper :)
06:08 < marcheu> hmm wait a minute
06:08 < marcheu> that was nvosdk's defaults
06:08 < marcheu> Xorg's defaults are
06:08 < marcheu> TRIG_128_BYTES
06:09 < marcheu> SIZE_32_BYTES
06:09 < marcheu> MAX_REQS_15
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06:13 < marcheu> not sure what MAX_REQS is for
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06:20 < marcheu> hmm probably the number of requests serviced before a context switch
06:20 < marcheu> so we can actually give different priorities to the contexts
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06:21 < marcheu> in hw, not by hacking the interrupt code to choose the fifo we want more often
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06:24 < darktama> hm, I should probably make my test code put a bit more stuff in the fifo - if you need to hit the trigger size before you get context switching
06:24 < marcheu> hehe, I modified it already
06:24 < marcheu> I put nops anyway
06:24 < darktama> ahh :)
06:25 < marcheu> not that putting anything is needed to trigger the fifo error
06:26 < darktama> at what point do you get the error?
06:26 < marcheu> you only need to init the 2nd fifo
06:26 < marcheu> and then you get a fifo error
06:26 < marcheu> no need to even touch the 2nd fifo's PUT
06:27 < darktama> hm that's interesting, what are you doing at FIFO init time now?
06:27 < marcheu> well, that's with the current git code
06:27 < marcheu> I'm adding a lot of fifo init code to it, we'll see
06:28 < marcheu> I suppose that RAMFC is not only a scratch area, but is only used by the card
06:28 < marcheu> otherwise I don't see how it could detect failure
06:28 < marcheu> s/only used/also used/
06:30 < darktama> I guess it must be, I don't see the point in having a scratch area just used by the driver living in the card's registers
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06:30 < marcheu> yup
06:31 < marcheu> plus you have to direct the card to it by giving its offset
06:31 < darktama> indeed
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06:50 < marcheu> darktama: anything agains renaming FIFO_INIT to FIFO_ALLOC ?
06:50 < darktama> nope, alloc is probably more correct anyway
06:50 < marcheu> then I'd like to rename pfifo_init to fifo_init which is the real name
06:51  * marcheu loves breking nouveau_drm.h because he always forget to install the latest header
06:52 < darktama> hehe, I like watching everyone who complains that the ddx won't compile :)
06:52 < marcheu> well my current changes remove the REINIT ioctl
06:52 < marcheu> I had forgotten to update nouveau_drm.h
06:53 < marcheu> and then the wrong ioctls would get called... pretty funny :)
06:53 < darktama> hehe, fun tracking that down too :)
07:00 < marcheu> also, why is nouveau_fifo_init called from nouveau_fifo_cleanup ?
07:00 < marcheu> I'd expect the state to stay
07:01 < darktama> the idea was to point back at an active channel
07:01 < marcheu> ah ok
07:01 < marcheu> I suppose we need a nouveau_fifo_free, even if we only use internally
07:04 < marcheu> also, do you mind if I move nouveau_dma_init to nouveau_fifo.c ?
07:04 < darktama> nope :)
07:04 < marcheu> it's mostly responsible for initializing the fifo stuff..
07:07 < marcheu> on second look, it only initializes fifo stuff
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12:58 < pmdata> marcheu> do you think I can test_interesting_regs() again? did you fix anything?
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14:20 < rem> yop
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14:50 < marcheu> pmdata: I didn't fix anything, but I'm really interested in the results so I might do it soonish
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14:53 < pmdata> marcheu> it is 0x400600,640 that hangs on my nv15 in interesting_regs, the others work
14:54 < marcheu> yup, I figured out as much on nv11
14:54 < marcheu> I'll have a fix in a moment
14:57 < marcheu> pmdata: should be fixed now
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15:08 < pmdata> Added dump in nv15pm if you need it
15:18 < pmdata> what exacly lies in these regs?
15:18 < marcheu> we don't always know, that's why I want dumps
15:18 < marcheu> there are the surface regs, and the irq regs ATM
15:19 < marcheu> but these are mostly regs used by the DDX, which I'd like to understand
15:31 < marcheu> pmdata: btw, any progress on understanding the DRI mess ?
15:31 < marcheu> pmdata: don't hesitate if you have questions btw
15:33 < pmdata> hum, I had some other stuff to do this week, I may come back to it
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15:45 < pmdata> would it be possible to draw some stuff that don't use texturing or any other required dma operation?
15:47 < marcheu> yes, you'd have to use the fifo #0 though
15:47 < marcheu> which means sharing it with X
15:49 < darktama> hmm, I wonder if it's worth hacking that into the ddx/mesa driver temporarily
15:50 < marcheu> that code would be pretty intricate
15:50 < darktama> yes, that's true
15:50 < marcheu> that's why context switch is top priority right now :)
15:52 < darktama> any luck with that yet? (well, since a few hours ago :P )
15:52 < marcheu> still writing code
15:52 < marcheu> I'm cleaning up the DRM fifo stuff
15:52 < darktama> quite a task :)
15:52 < marcheu> things like nouveau_fifo_enable have to go
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18:16 < marcheu> darktama: you around ?
18:16 < marcheu> I have a doubt about the NV_PFIFO_CACH1_DMAS value
18:16 < darktama> yup
18:16 < marcheu> as seen in the drm
18:16 < marcheu> it says NV_PFIFO_CACH1_DMAS is 3220, I think 3228
18:18 < marcheu> it looks like an oversight during the ddx -> drm conversion
18:19 < darktama> hmm, that's quite possible
18:19 < darktama> the names, I stole from haiku.. which calls 0x3220 DMAS
18:19 < marcheu> ah
18:19 < marcheu> so I think haiku is wrong, because both nv10reg and nvosdk say the opposite
18:20 < darktama> yup, I was just looking at nvxref.h
18:21 < darktama> it depends on what haiku means by DMAS I guess
18:22 < marcheu> well, we have DMA_STATUS to name as well..
18:22 < darktama> does the original nv ddx write 0x3220 or 0x3228 there?  I don't see why it'd be writing 0x3228
18:22 < marcheu> it writes 3220
18:23 < marcheu> hmm s/DMA_STATUS/DMA_STATE/
18:24 < darktama> btw, do you know what is meant by PUSH_ACCESS_ENABLED/DISABLED?
18:24 < darktama> (looking at 0x3220)
18:24 < marcheu> hmm, where ?
18:24 < marcheu> no, all I know is X has it to 0, nvosdk to 1
18:25 < darktama> hm, we write 1 to it
18:25 < marcheu> hmm maybe it's the opposite
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18:25 < marcheu> yeah, 3200 is 1 for both
18:26 < marcheu> yeah, others ar the same as well... must have dreamed it
18:26 < darktama> hehe
18:26 < darktama> I'm still not sure I understand what the relation is between a FIFO ("push buffer" in nvidia speak), and CACHE1
18:27 < darktama> from looking at FIFO error handling, some PFIFO regs are filled with commands from the FIFO (CACHE1_GET/PUT indexes into them)
18:28 < darktama> 0x3800/0x3804 for older cards, 0x90000/0x90004 for at least NV40
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18:29 < marcheu> hmm where did you see that ?
18:30 < darktama> the 0x3800/0x3804?  nvosdk's FIFO error handler, it's how it determines the method/data that caused the error.. NV40's seems to be starting from 0x90000, from the dumps it looks like a replica of what's in the FIFO
18:30 < marcheu> yeah but for nv40 ?
18:31 < darktama> NV40 I found through deliberately causing errors and looking at PFIFO dumps :S
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18:57 < marcheu> hmm
18:58 < marcheu> now that I have added that fifo init code, I get 4 errors interrupts at once :)
18:58 < marcheu> not sure if I can say the situation improves
18:58 < darktama> hahaha, good effort :P
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19:03 < marcheu> hmm I got a [drm] NV: unknown PFIFO interrupt. status=0x00001000
19:04 < marcheu> seems to be _PUSHER_PENDING
19:04 < marcheu> no idea what that means
19:04 < darktama> hm, that's one of the one's I've had before.. no idea what it's purpose is though
19:04 < darktama> nvosdk doesn't do much at all for it
19:07 < marcheu> seems context switching related
19:07 < marcheu> only appears when you enable the context switch interrupt bit
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--- Log closed Вск Сен 24 00:00:46 2006
